TY - GEN

T1 - Cost modeling and analysis for interposer-based three-dimensional IC

AU - Chou, Ying Wen

AU - Chen, Po Yuan

AU - Lee, Mincent

AU - Wu, Cheng Wen

PY - 2012/8/20

Y1 - 2012/8/20

N2 - Three-dimensional (3D) integration has recently become a popular technology for integrated circuits (IC). 3D IC with the passive silicon interposer is currently the main trend in the industry, especially for processor-memory integration. Evaluating the economic efficiency of test operations in the interposer-based 3D IC thus is important. We propose a cost model for the Die-to-Wafer (D2W) and Die-to-Die (D2D) stacking, including manufacturing cost and test cost. A tool which is based on the proposed cost model is developed. We use this tool for cost analysis and for finding the most cost effective test flow. The results show that, in some applications, test flows including the iterative known-good stack (KGS) test and the pre-bond interposer test significantly reduce the cost, when the KGS test yield is lower than 98.2% and the pre-bond interposer test yield is lower than 99.38%. A Shmoo plot is depicted to show the lower bound of the yield of the final package level test, given the number of stacked dies and the final yield. For different applications, the proposed model evaluates the critical yield or cost values, which helps the designers to determine the most cost effective test flow and the system architecture.

AB - Three-dimensional (3D) integration has recently become a popular technology for integrated circuits (IC). 3D IC with the passive silicon interposer is currently the main trend in the industry, especially for processor-memory integration. Evaluating the economic efficiency of test operations in the interposer-based 3D IC thus is important. We propose a cost model for the Die-to-Wafer (D2W) and Die-to-Die (D2D) stacking, including manufacturing cost and test cost. A tool which is based on the proposed cost model is developed. We use this tool for cost analysis and for finding the most cost effective test flow. The results show that, in some applications, test flows including the iterative known-good stack (KGS) test and the pre-bond interposer test significantly reduce the cost, when the KGS test yield is lower than 98.2% and the pre-bond interposer test yield is lower than 99.38%. A Shmoo plot is depicted to show the lower bound of the yield of the final package level test, given the number of stacked dies and the final yield. For different applications, the proposed model evaluates the critical yield or cost values, which helps the designers to determine the most cost effective test flow and the system architecture.

UR - http://www.scopus.com/inward/record.url?scp=84864996596&partnerID=8YFLogxK

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U2 - 10.1109/VTS.2012.6231088

DO - 10.1109/VTS.2012.6231088

M3 - Conference contribution

AN - SCOPUS:84864996596

SN - 9781467310741

T3 - Proceedings of the IEEE VLSI Test Symposium

SP - 108

EP - 113

BT - Proceedings - 2012 30th IEEE VLSI Test Symposium, VTS 2012

T2 - 2012 30th IEEE VLSI Test Symposium, VTS 2012

Y2 - 23 April 2012 through 26 April 2012

ER -