Cost modeling and analysis for interposer-based three-dimensional IC

Ying Wen Chou, Po Yuan Chen, Mincent Lee, Cheng Wen Wu

研究成果: Conference contribution

11 引文 斯高帕斯(Scopus)

摘要

Three-dimensional (3D) integration has recently become a popular technology for integrated circuits (IC). 3D IC with the passive silicon interposer is currently the main trend in the industry, especially for processor-memory integration. Evaluating the economic efficiency of test operations in the interposer-based 3D IC thus is important. We propose a cost model for the Die-to-Wafer (D2W) and Die-to-Die (D2D) stacking, including manufacturing cost and test cost. A tool which is based on the proposed cost model is developed. We use this tool for cost analysis and for finding the most cost effective test flow. The results show that, in some applications, test flows including the iterative known-good stack (KGS) test and the pre-bond interposer test significantly reduce the cost, when the KGS test yield is lower than 98.2% and the pre-bond interposer test yield is lower than 99.38%. A Shmoo plot is depicted to show the lower bound of the yield of the final package level test, given the number of stacked dies and the final yield. For different applications, the proposed model evaluates the critical yield or cost values, which helps the designers to determine the most cost effective test flow and the system architecture.

原文English
主出版物標題Proceedings - 2012 30th IEEE VLSI Test Symposium, VTS 2012
頁面108-113
頁數6
DOIs
出版狀態Published - 2012 八月 20
事件2012 30th IEEE VLSI Test Symposium, VTS 2012 - Hyatt Maui, HI, United States
持續時間: 2012 四月 232012 四月 26

出版系列

名字Proceedings of the IEEE VLSI Test Symposium

Conference

Conference2012 30th IEEE VLSI Test Symposium, VTS 2012
國家/地區United States
城市Hyatt Maui, HI
期間12-04-2312-04-26

All Science Journal Classification (ASJC) codes

  • 電腦科學應用
  • 電氣與電子工程

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