Counter-based output selection for test response compaction

Wei Cheng Lien, Kuen-Jong Lee, Tong Yu Hsieh, Krishnendu Chakrabarty, Yu Hua Wu

研究成果: Article同行評審

7 引文 斯高帕斯(Scopus)

摘要

Output selection is a recently proposed test response compaction method, where only a subset of output response bits is selected for observation. It can achieve zero aliasing, full X-tolerance, and high diagnosability. One critical issue for output selection is how to implement the selection hardware. In this paper, we present a counter-based output selection scheme that employs only a counter and a multiplexer, hence involving very small area overhead and simple test control. The proposed scheme is ATPG-independent and thus can easily be incorporated into a typical design flow. Two efficient output selection algorithms are presented to determine the desired output responses, one using a single counter operation for simpler test control and the other using more counter operations for achieving a better test-response reduction ratio. Experimental results show that for stuck-at faults in large ISCAS'89 and ITC'99 benchmark circuits, 48%-90% reduction ratios on test responses can be achieved with only one counter and one multiplexer employed. Even better results, i.e., 76%-95% reductions, can be obtained for transition faults. It is also shown that the diagnostic resolution of this method is almost the same as that achieved by observing all output responses.

原文English
文章編號6387700
頁(從 - 到)152-164
頁數13
期刊IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
32
發行號1
DOIs
出版狀態Published - 2013 一月 7

All Science Journal Classification (ASJC) codes

  • 軟體
  • 電腦繪圖與電腦輔助設計
  • 電氣與電子工程

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