Counterdoped pocket thickness optimization of gate-on-source-only tunnel FETs

Kuo-Hsing Kao, Anne S. Verhulst, William G. Vandenberghe, Kristin De Meyer

研究成果: Article同行評審

28 引文 斯高帕斯(Scopus)

摘要

The optimized tunnel field-effect transistor with a gate electrode overlapping the source region exhibits a steeper subthreshold swing (SS) and a higher on-state tunneling current than the transistor with a gate on the channel only. In the presence of a counterdoped pocket in the source region underneath the gate electrode, the vertical tunneling component dominates over the unwanted lateral tunneling component, and the performance variability is reduced compared to its no-pocket configuration. The optimal pocket thickness, which is a tradeoff between realistic gate work function and the desired SS, is dependent on the bandgap, electron or hole effective mass, permittivity, and tunneling orientation of semiconductor materials, as analyzed in detail in this paper. A numerical procedure is provided to determine the optimal pocket thickness for arbitrary semiconductor materials.

原文English
文章編號6359896
頁(從 - 到)6-12
頁數7
期刊IEEE Transactions on Electron Devices
60
發行號1
DOIs
出版狀態Published - 2013 一月 1

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 電氣與電子工程

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