Cycle time reduction for semiconductor wafer fabrication facilities

Doron Meyersdorf, Taho Yang

研究成果: Paper同行評審

22 引文 斯高帕斯(Scopus)

摘要

The issue of cycle time reduction and its impact on a company's competitive edge has been gaining considerable attention recently. Generally speaking, shorter cycle times result in better customer satisfaction, lower work-in-process (WIP), higher yield, and better capacity given tool inventory and facility constraints. This paper provides a brief review of key concepts related to cycle time and describes a methodology for cycle time reduction projects in semiconductor wafer fabrication facilities, including the critically important implementation road map step. Finally, a case study is presented to illustrate the effectiveness and potential gains of the proposed cycle time reduction methodology.

原文English
頁面418-423
頁數6
出版狀態Published - 1997 十二月 1
事件Proceedings of the 1997 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop - Cambridge, MA, USA
持續時間: 1997 九月 101997 九月 12

Other

OtherProceedings of the 1997 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop
城市Cambridge, MA, USA
期間97-09-1097-09-12

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Engineering(all)
  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering

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