DArT: A component-based DRAM area, power, and timing modeling tool

Hsiu Chuan Shih, Pei Wen Luo, Jen Chieh Yeh, Shu Yen Lin, Ding Ming Kwai, Shih Lien Lu, Andre Schaefer, Cheng Wen Wu

研究成果: Article同行評審

11 引文 斯高帕斯(Scopus)

摘要

DRAM renovation calls for a holistic architecture exploration to cope with bandwidth growth and latency reduction need. In this paper, we present DRAM area power timing (DArT), a DRAM area, power, and timing modeling tool, for array assembly and interface customization. Through proper design abstraction, our component-based modeling approach provides increased flexibility and higher accuracy, making DArT suitable for DRAM architecture exploration and performance estimation. We validate the accuracy of DArT with respect to the physical layout and circuit simulation of an industrial 68 nm commodity DRAM device as a reference. The experiment results show that the maximum deviations from the reference design, in terms of area, timing, and power, are 3.2%, 4.92%, and 1.73%, respectively. For an architectural projection by porting it to a 45 nm process, the maximum deviations are 3.4%, 3.42%, and 8.57%, respectively. The combination of modeling performance, flexibility, and accuracy of DArT allows us to easily explore new DRAM architectures in the future, including 3-D stacked DRAM.

原文English
文章編號6879579
頁(從 - 到)1356-1369
頁數14
期刊IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
33
發行號9
DOIs
出版狀態Published - 2014 一月 1

All Science Journal Classification (ASJC) codes

  • 軟體
  • 電腦繪圖與電腦輔助設計
  • 電氣與電子工程

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