Dataflow-Aware Macro Placement Based on Simulated Evolution Algorithm for Mixed-Size Designs

Jai Ming Lin, You Lun Deng, Ya Chu Yang, Jia Jian Chen, Po Chen Lu

研究成果: Article同行評審

2 引文 斯高帕斯(Scopus)

摘要

This article proposes a novel approach to handle macro placement. Previous works usually apply the simulated annealing (SA) algorithm to handle this problem. However, the SA-based approaches usually have difficulty in handling preplaced macros and require longer runtime. To resolve these problems, we propose a macro placement procedure based on the corner stitching data structure and then apply an efficient and effective simulated evolution algorithm to further refine placement results. In order to relieve local routing congestion, we propose to expand areas of movable macros according to the design hierarchy before applying the macro placement algorithm. Finally, we extend our macro placement methodology to consider dataflow constraint so that dataflow-related macros can be placed at close locations. The experimental results show that our approach obtains a better solution than a previous macro placement algorithm and a tool. Besides, placement quality can be further improved when the dataflow constraint is considered.

原文English
文章編號9360844
頁(從 - 到)973-984
頁數12
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
29
發行號5
DOIs
出版狀態Published - 2021 5月

All Science Journal Classification (ASJC) codes

  • 軟體
  • 硬體和架構
  • 電氣與電子工程

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