DC and 1/f noise characteristics of strained-Si nMOSFETs using chemical-mechanical-polishing technique

Hau Yu Lin, San Lein Wu, Shoou Jinn Chang, Cheng Wen Kuo, Yen Ping Wang, Shang Chao Hung

研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)

摘要

Utilizing chemical-mechanical-polishing (CMP) technique to reduce oxide interface defects and roughness induced from SiGe virtual substrate in strained-Si nMOSFETs has been investigated. Due to the smoother SiO2/Si interface, an additional 3.5% driving current and 11% transconductance enhancements are found in strained-Si devices with a gate length = 0.5 μm on CMP-treated SiGe virtual substrate, compared to strained-Si devices without CMP process. Moreover, strained-Si devices with CMP process exhibit the lowest 1/f noise. Under larger gate voltage overdrive, the enhancements become more obvious indicating that the CMP process provides a smoother surface of the strained-Si/SiGe structure.

原文English
頁(從 - 到)905-908
頁數4
期刊Solid-State Electronics
53
發行號8
DOIs
出版狀態Published - 2009 八月

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 凝聚態物理學
  • 電氣與電子工程
  • 材料化學

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