Utilizing chemical-mechanical-polishing (CMP) technique to reduce oxide interface defects and roughness induced from SiGe virtual substrate in strained-Si nMOSFETs has been investigated. Due to the smoother SiO2/Si interface, an additional 3.5% driving current and 11% transconductance enhancements are found in strained-Si devices with a gate length = 0.5 μm on CMP-treated SiGe virtual substrate, compared to strained-Si devices without CMP process. Moreover, strained-Si devices with CMP process exhibit the lowest 1/f noise. Under larger gate voltage overdrive, the enhancements become more obvious indicating that the CMP process provides a smoother surface of the strained-Si/SiGe structure.
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