DC and 1/f noise characteristics of strained-Si nMOSFETs using chemical-mechanical-polishing technique

Hau Yu Lin; San Lein Wu; Shoou Jinn Chang; Cheng Wen Kuo; Yen Ping Wang; Shang Chao Hung

doi:10.1016/j.sse.2009.04.019

DC and 1/f noise characteristics of strained-Si nMOSFETs using chemical-mechanical-polishing technique

Hau Yu Lin, San Lein Wu, Shoou Jinn Chang, Cheng Wen Kuo, Yen Ping Wang, Shang Chao Hung

微電子工程研究所

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

摘要

Utilizing chemical-mechanical-polishing (CMP) technique to reduce oxide interface defects and roughness induced from SiGe virtual substrate in strained-Si nMOSFETs has been investigated. Due to the smoother SiO₂/Si interface, an additional 3.5% driving current and 11% transconductance enhancements are found in strained-Si devices with a gate length = 0.5 μm on CMP-treated SiGe virtual substrate, compared to strained-Si devices without CMP process. Moreover, strained-Si devices with CMP process exhibit the lowest 1/f noise. Under larger gate voltage overdrive, the enhancements become more obvious indicating that the CMP process provides a smoother surface of the strained-Si/SiGe structure.

原文	English
頁（從 - 到）	905-908
頁數	4
期刊	Solid-State Electronics
卷	53
發行號	8
DOIs	https://doi.org/10.1016/j.sse.2009.04.019
出版狀態	Published - 2009 8月

All Science Journal Classification (ASJC) codes

電子、光磁材料
凝聚態物理學
電氣與電子工程
材料化學

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10.1016/j.sse.2009.04.019

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title = "DC and 1/f noise characteristics of strained-Si nMOSFETs using chemical-mechanical-polishing technique",

abstract = "Utilizing chemical-mechanical-polishing (CMP) technique to reduce oxide interface defects and roughness induced from SiGe virtual substrate in strained-Si nMOSFETs has been investigated. Due to the smoother SiO2/Si interface, an additional 3.5% driving current and 11% transconductance enhancements are found in strained-Si devices with a gate length = 0.5 μm on CMP-treated SiGe virtual substrate, compared to strained-Si devices without CMP process. Moreover, strained-Si devices with CMP process exhibit the lowest 1/f noise. Under larger gate voltage overdrive, the enhancements become more obvious indicating that the CMP process provides a smoother surface of the strained-Si/SiGe structure.",

author = "Lin, {Hau Yu} and Wu, {San Lein} and Chang, {Shoou Jinn} and Kuo, {Cheng Wen} and Wang, {Yen Ping} and Hung, {Shang Chao}",

note = "Funding Information: This work was partially supported by the Science Council under Contract NSC 96-2221-E-230-022. ",

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T1 - DC and 1/f noise characteristics of strained-Si nMOSFETs using chemical-mechanical-polishing technique

AU - Lin, Hau Yu

AU - Wu, San Lein

AU - Chang, Shoou Jinn

AU - Kuo, Cheng Wen

AU - Wang, Yen Ping

AU - Hung, Shang Chao

N1 - Funding Information: This work was partially supported by the Science Council under Contract NSC 96-2221-E-230-022.

PY - 2009/8

Y1 - 2009/8

N2 - Utilizing chemical-mechanical-polishing (CMP) technique to reduce oxide interface defects and roughness induced from SiGe virtual substrate in strained-Si nMOSFETs has been investigated. Due to the smoother SiO2/Si interface, an additional 3.5% driving current and 11% transconductance enhancements are found in strained-Si devices with a gate length = 0.5 μm on CMP-treated SiGe virtual substrate, compared to strained-Si devices without CMP process. Moreover, strained-Si devices with CMP process exhibit the lowest 1/f noise. Under larger gate voltage overdrive, the enhancements become more obvious indicating that the CMP process provides a smoother surface of the strained-Si/SiGe structure.

AB - Utilizing chemical-mechanical-polishing (CMP) technique to reduce oxide interface defects and roughness induced from SiGe virtual substrate in strained-Si nMOSFETs has been investigated. Due to the smoother SiO2/Si interface, an additional 3.5% driving current and 11% transconductance enhancements are found in strained-Si devices with a gate length = 0.5 μm on CMP-treated SiGe virtual substrate, compared to strained-Si devices without CMP process. Moreover, strained-Si devices with CMP process exhibit the lowest 1/f noise. Under larger gate voltage overdrive, the enhancements become more obvious indicating that the CMP process provides a smoother surface of the strained-Si/SiGe structure.

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DC and 1/f noise characteristics of strained-Si nMOSFETs using chemical-mechanical-polishing technique

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