With the increase in design complexity and test data volume, compressed tests together with on-chip test decompression hardware such as Embedded Deterministic Test (EDTTM) are widely used in industry in order to reduce test cost. One of the challenges of such Design-for-Test (DFT) technology is to determine a set of optimal parameters such as the number of scan chains, scan channels, power budget, etc. such that it can reach the highest test coverage with a minimum amount of test data volume whilst satisfying various other constraints. To achieve the optimal compression configuration quickly, in this work deep learning technology based on Tensorflow is explored to estimate the test coverage and the data volume for a design when employing EDT under a given set of circuit parameters. Based on the estimated data, the optimal test architecture is also predicted, yielding a more efficient approach compared to the currently used trial-and-error methods. To demonstrate the advantages of our deep learning approach over the currently used utility, we present experimental data for eight industrial designs.