Defect oriented fault analysis for SRAM

Rei Fu Huang, Yung Fa Chou, Cheng Wen Wu

研究成果: Conference contribution

19 引文 斯高帕斯(Scopus)

摘要

Fault analysis is an important step in establishing detailed fault models or subsequent diagnostics and debugging of a semiconductor memory product. We have performed defect injection in the memory cell array of an industrial SRAM circuit and analyzed the faulty behavior with respect to each defect injected. We found that although some of the defects can be mapped to existing fault models, there are many defects that result in unmodeled faults. Moreover, a defect may exhibit a different faulty behavior at a different location in the cell array. The voltage and temperature parameters can also change the faulty behavior. The simulation results show that almost all open and short defects lead to stuck-at faults, transition faults, and data retention faults.

原文English
主出版物標題Proceedings - 12th Asian Test Symposium, ATS 2003
發行者IEEE Computer Society
頁面256-261
頁數6
ISBN(電子)0769519512
DOIs
出版狀態Published - 2003 1月 1
事件12th Asian Test Symposium, ATS 2003 - Xi'an, China
持續時間: 2003 11月 162003 11月 19

出版系列

名字Proceedings of the Asian Test Symposium
2003-January
ISSN(列印)1081-7735

Other

Other12th Asian Test Symposium, ATS 2003
國家/地區China
城市Xi'an
期間03-11-1603-11-19

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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