Delay and power model for current-mode signaling in deep submicron global interconnects

Rizwan Bashirullah, Wentai Liu, Ralph Cavin

研究成果: Conference article同行評審

18 引文 斯高帕斯(Scopus)

摘要

In this paper, closed-form expressions of delay and power dissipation based on the effective lumped element resistance and capacitance approximation of distributed RC lines are presented. A new closed-form solution of delay under step input excitation is developed, exhibiting an accuracy that is within 5% for a wide range of parameters. The usefulness of this solution is that both resistive and capacitive load termination is accurately modeled for use in current mode signaling. A new power dissipation model for current-mode signaling is developed to understand the design tradeoffs between current and voltage sensing. Based on these formulations, a comparison between voltage-mode repeater insertion technique and current-mode signaling over long, global deep submicron interconnects is presented.

原文English
頁(從 - 到)513-516
頁數4
期刊Proceedings of the Custom Integrated Circuits Conference
出版狀態Published - 2002
事件IEEE 2002 Custom Integrated Circuits Conference - Orlando, FL, United States
持續時間: 2002 5月 122002 5月 15

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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