Demonstration of a novel multilevel storage scheme for phase change memory using a parameterized HSPICE model

D. S. Chao, C. H. Lien, Y. B. Liao, M. H. Chiang, P. H. Yen, M. J. Chen, P. C. Chiang, M. J. Tsai

研究成果: Conference contribution

摘要

A novel scheme for PCM multilevel storage, namely the stacked PCM, was proposed in this study. Multiple PCM cells having various programmed volumes are vertically stacked and connected in series to constitute the architecture of the stacked PCM. To simulate the coupling programming characteristics of the stacked PCM, a parameterized PCM HSPICE model was established on the basis of the specific device parameters extracted from the fabricated double confined cells. The results indicate that 2 bits/cell storage can be accomplished by the stacked PCM with three interconnected cells. The simulated step-like R-I curves demonstrate the desirable attributes of direct overwrite capability and larger programming margin. The phenomena of multiple snapbacks can also be observed from the simulated I-V characteristics. Relying on the simulated results by the PCM HSPICE model, the stacked PCM could be one feasible approach for accomplishing multilevel storage in PCM.

原文English
主出版物標題China Semiconductor Technology International Conference 2012, CSTIC 2012
頁面1303-1310
頁數8
版本1
DOIs
出版狀態Published - 2012 十二月 1
事件China Semiconductor Technology International Conference 2012, CSTIC 2012 - Shanghai, China
持續時間: 2012 三月 182012 三月 19

出版系列

名字ECS Transactions
號碼1
44
ISSN(列印)1938-5862
ISSN(電子)1938-6737

Other

OtherChina Semiconductor Technology International Conference 2012, CSTIC 2012
國家/地區China
城市Shanghai
期間12-03-1812-03-19

All Science Journal Classification (ASJC) codes

  • 工程 (全部)

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