Dependence of DC parameters on layout and low-frequency noise behavior in strained-si nMOSFETs fabricated by stress-memorization technique

Yao Tsung Huang, San Lein Wu, Shoou-Jinn Chang, Cheng Wen Kuo, Ya Ting Chen, Yao Chin Cheng, Osbert Cheng

研究成果: Article

7 引文 (Scopus)

摘要

The impact of stress-memorization technique (SMT)-induced tensile strain on the layout dependence of nMOSFET characteristics is investigated. It is found that the incorporation of the SMT process provides up to 12% improvement in transconductance and 9% enhancement in on-state current for nMOSFETs with a source/drain length (LS/D) of 1.76 μmand W = 0.5. The characteristics of the SMT device become more sensitive to the layout geometry as LS/D and W are down to 0.5 and 0.25 μm, respectively. Moreover, low-frequency measurements reveal that the interface quality of the SMT device is the same as that of the control devices. Furthermore, it is found that the mechanism of 1 noise in the SMT device can be properly interpreted by the unified model.

原文English
文章編號5439695
頁(從 - 到)500-502
頁數3
期刊IEEE Electron Device Letters
31
發行號5
DOIs
出版狀態Published - 2010 五月 1

指紋

Tensile strain
Transconductance
Geometry

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

引用此文

Huang, Yao Tsung ; Wu, San Lein ; Chang, Shoou-Jinn ; Kuo, Cheng Wen ; Chen, Ya Ting ; Cheng, Yao Chin ; Cheng, Osbert. / Dependence of DC parameters on layout and low-frequency noise behavior in strained-si nMOSFETs fabricated by stress-memorization technique. 於: IEEE Electron Device Letters. 2010 ; 卷 31, 編號 5. 頁 500-502.
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abstract = "The impact of stress-memorization technique (SMT)-induced tensile strain on the layout dependence of nMOSFET characteristics is investigated. It is found that the incorporation of the SMT process provides up to 12{\%} improvement in transconductance and 9{\%} enhancement in on-state current for nMOSFETs with a source/drain length (LS/D) of 1.76 μmand W = 0.5. The characteristics of the SMT device become more sensitive to the layout geometry as LS/D and W are down to 0.5 and 0.25 μm, respectively. Moreover, low-frequency measurements reveal that the interface quality of the SMT device is the same as that of the control devices. Furthermore, it is found that the mechanism of 1 noise in the SMT device can be properly interpreted by the unified model.",
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Dependence of DC parameters on layout and low-frequency noise behavior in strained-si nMOSFETs fabricated by stress-memorization technique. / Huang, Yao Tsung; Wu, San Lein; Chang, Shoou-Jinn; Kuo, Cheng Wen; Chen, Ya Ting; Cheng, Yao Chin; Cheng, Osbert.

於: IEEE Electron Device Letters, 卷 31, 編號 5, 5439695, 01.05.2010, p. 500-502.

研究成果: Article

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AU - Chen, Ya Ting

AU - Cheng, Yao Chin

AU - Cheng, Osbert

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