TY - GEN
T1 - Design and analysis of an interleave controlled series buck converter with low load current ripple
AU - Ko, Cai Yang
AU - Liang, Tsorng-Juu
AU - Chen, Kai Hui
AU - Chen, Jiann-Fuh
PY - 2010/12/1
Y1 - 2010/12/1
N2 - In this paper, a novel high step-down DC-DC converter is proposed. The voltage conversion gain of this converter is Vo/Vin=D 2. By using the interleaved control, the output current ripple is reduced and the transient response is improved. The operating principles and small-signal analysis are discussed. Finally, a laboratory prototype circuit with input voltage 12 V and output 1.5 V / 50 A is implemented to verify the proposed converter.
AB - In this paper, a novel high step-down DC-DC converter is proposed. The voltage conversion gain of this converter is Vo/Vin=D 2. By using the interleaved control, the output current ripple is reduced and the transient response is improved. The operating principles and small-signal analysis are discussed. Finally, a laboratory prototype circuit with input voltage 12 V and output 1.5 V / 50 A is implemented to verify the proposed converter.
UR - http://www.scopus.com/inward/record.url?scp=79959211876&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79959211876&partnerID=8YFLogxK
U2 - 10.1109/APCCAS.2010.5774834
DO - 10.1109/APCCAS.2010.5774834
M3 - Conference contribution
AN - SCOPUS:79959211876
SN - 9781424474561
T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
SP - 672
EP - 675
BT - Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
T2 - 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Y2 - 6 December 2010 through 9 December 2010
ER -