Design and fabrication of 0/1-level RF-via interconnect for RF-MEMS packaging applications

Li Han Hsu, Wei Cheng Wu, Edward Yi Chang, Herbert Zirath, Yun Chi Wu, Chin Te Wang, Ching Ting Lee

研究成果: Article同行評審

7 引文 斯高帕斯(Scopus)

摘要

This paper presents the parametric study of RF-via (0-level) and flip-chip bump (1-level) transitions for applications of packaging coplanar RF-MEMS devices. The key parameters were found to be the bumps' and vias' positions and the overlap of the metal pads, which should be carefully considered in the entire two levels of packages. The length of the backside transmission line, determining the MEMS substrate area, showed minor influence on the interconnect performance. With the experimental results, the design rules have been developed and established. The optimized interconnect structure for the two levels of packages demonstrates the return loss beyond 15 dB and the insertion loss within 0.6 dB from dc to 60 GHz.

原文English
文章編號5345704
頁(從 - 到)30-36
頁數7
期刊IEEE Transactions on Advanced Packaging
33
發行號1
DOIs
出版狀態Published - 2010 二月

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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