A pipelining fuzzy inference chip with a self-tunable knowledge base is presented in this paper. Up to 49 rules are inferred in parallel in the chip, and the memory size of its knowledge (rule) base is only 84 bytes since the memory-efficient and adjustable fuzzy rule format as well as the dynamic rule generating circuits are used. Based on these mechanism and a rule weight tuner, the possibility of narrowing, widening, moving, amplifying, and/or dampening the membership functions is provided in it, and makes the inference process self-adaptive. A three-stage pipeline in the parallel inference architecture let the chip very fast. It can yield an inference rate of 467K inferences/sec operating at a clock rate of 30 MHz.
|出版狀態||Published - 1995 一月 1|
|事件||Proceedings of the 1995 IEEE International Conference on Fuzzy Systems. Part 1 (of 5) - Yokohama, Jpn|
持續時間: 1995 三月 20 → 1995 三月 24
|Other||Proceedings of the 1995 IEEE International Conference on Fuzzy Systems. Part 1 (of 5)|
|期間||95-03-20 → 95-03-24|
All Science Journal Classification (ASJC) codes