Design and implementation of a two-dimensional fast Fourier transform chip.

William T. Krakow, William E. Batchelor, Wentai Liu, Thomas Hildebrandt, Thomas Hughes, Tong fei Yeh, Roberto Salama, Gwegwo Mei

研究成果: Conference article同行評審

摘要

A description is given of a rasterized, pipelined architecture for performing a two-dimensional fast Fourier transformation (2DFFT). A chip has been designed for implementing this architecture in 1.25-μm CMOS. Each chip consists of 152 transistors on a 9-mm die. The chips operate at a clock speed of 10 MHz and process a 256 × 256-pixel image at a real-time frame rate of 30 Hz. Each chip has input and output data formats consisting of rasterized streams of 22-bit fixed-point complex numbers. The authors present the chip architecture and describe the design of its constituent units. On-chip storage of the sine/cosine factors and the absence of corner-turning memory are the most novel features.

原文English
頁(從 - 到)8.4/1-4
期刊Proceedings of the Custom Integrated Circuits Conference
出版狀態Published - 1988

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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