TY - GEN
T1 - Design and implementation of window delay-line ADC for low-power DC-DC SMPS
AU - Chen, Huei Shan
AU - Yang, Chun Hung
AU - Tsai, Chien Hung
AU - Li, Guan Lin
PY - 2012
Y1 - 2012
N2 - A window delay-line analog-to-digital converter (ADC) with programmable resolutions for digitally-controlled switch-mode power supplies (SMPS) used in low-power portable applications is proposed in this paper. Due to its simple, low-power architecture and small silicon area, this ADC can be fully integrated with a digital controller. The proposed ADC quantizes the output converter voltage within a window of the reference voltage. The ADC has been fabricated in a TSMC 0.18μm CMOS technology and verified as a part of a 976.56 KHz, 3.6 to 1.2 V buck DC-DC converter.
AB - A window delay-line analog-to-digital converter (ADC) with programmable resolutions for digitally-controlled switch-mode power supplies (SMPS) used in low-power portable applications is proposed in this paper. Due to its simple, low-power architecture and small silicon area, this ADC can be fully integrated with a digital controller. The proposed ADC quantizes the output converter voltage within a window of the reference voltage. The ADC has been fabricated in a TSMC 0.18μm CMOS technology and verified as a part of a 976.56 KHz, 3.6 to 1.2 V buck DC-DC converter.
UR - http://www.scopus.com/inward/record.url?scp=84866725906&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84866725906&partnerID=8YFLogxK
U2 - 10.1109/COMPEL.2012.6251735
DO - 10.1109/COMPEL.2012.6251735
M3 - Conference contribution
AN - SCOPUS:84866725906
SN - 9781424493739
T3 - 2012 IEEE 13th Workshop on Control and Modeling for Power Electronics, COMPEL 2012
BT - 2012 IEEE 13th Workshop on Control and Modeling for Power Electronics, COMPEL 2012
T2 - 2012 IEEE 13th Workshop on Control and Modeling for Power Electronics, COMPEL 2012
Y2 - 10 July 2012 through 13 July 2012
ER -