Design and implementation of window delay-line ADC for low-power DC-DC SMPS

Huei Shan Chen, Chun Hung Yang, Chien Hung Tsai, Guan Lin Li

研究成果: Conference contribution

5 引文 斯高帕斯(Scopus)

摘要

A window delay-line analog-to-digital converter (ADC) with programmable resolutions for digitally-controlled switch-mode power supplies (SMPS) used in low-power portable applications is proposed in this paper. Due to its simple, low-power architecture and small silicon area, this ADC can be fully integrated with a digital controller. The proposed ADC quantizes the output converter voltage within a window of the reference voltage. The ADC has been fabricated in a TSMC 0.18μm CMOS technology and verified as a part of a 976.56 KHz, 3.6 to 1.2 V buck DC-DC converter.

原文English
主出版物標題2012 IEEE 13th Workshop on Control and Modeling for Power Electronics, COMPEL 2012
DOIs
出版狀態Published - 2012 十月 1
事件2012 IEEE 13th Workshop on Control and Modeling for Power Electronics, COMPEL 2012 - Kyoto, Japan
持續時間: 2012 七月 102012 七月 13

出版系列

名字2012 IEEE 13th Workshop on Control and Modeling for Power Electronics, COMPEL 2012

Other

Other2012 IEEE 13th Workshop on Control and Modeling for Power Electronics, COMPEL 2012
國家Japan
城市Kyoto
期間12-07-1012-07-13

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Modelling and Simulation

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