Design and test of a scalable security processor

Chih Pin Su, Chen Hsing Wang, Kuo Liang Cheng, Chih Tsun Huang, Cheng Wen Wu

研究成果: Conference contribution

7 引文 斯高帕斯(Scopus)

摘要

This paper presents a security processor to accelerate cryptographic processing in modern security applications. Our security processor is capable of popular cryptographic functions such as RSA, AES, hashing and random number generation, etc. With proposed Crypto-DMA controller, data gathering and scattering become flexible for security processing, using a simple descriptor-based programming model. The architecture of the security processor with its core-based platform is scalable and configurable for security variations in performance, cost and power consumption. Different number of data channels and crypto-engines can be used to meet the specifications. In addition, a DFT platform is also implemented for the design-test integration. The security processor has been fabricated with 0.18μm CMOS technology, The core area is 3.899mm times; 2.296mm (525K gates approximately) and the operating clock rate is 83MHz.

原文English
主出版物標題Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
頁面372-375
頁數4
出版狀態Published - 2005 十二月 1
事件2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China
持續時間: 2005 一月 182005 一月 21

出版系列

名字Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
1

Other

Other2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
國家/地區China
城市Shanghai
期間05-01-1805-01-21

All Science Journal Classification (ASJC) codes

  • 電腦科學應用
  • 電腦繪圖與電腦輔助設計
  • 電氣與電子工程

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