Design and Test Rules for CMOS Circuits to Facilitate IDDQ Testing of Bridging Faults

Kuen Jong Lee, Melvin A. Breuer

研究成果: Article同行評審

28 引文 斯高帕斯(Scopus)


IDDQ testing, or current supply monitoring (CSM), is an efficient and effective method for detecting CMOS bridging faults (BF’s). The applicability of this technique, hoever, requires careful examination. In this paper all possible BF’s between any two circuit nodes are considered, where a circuit node may be the drain, source, or gate terminal of a transistor. We first give several examples to show that under certain circumstances CSM cannot give correct test results. A circuit partitioning model is then described and a minimal set of design and test rules is presented. This set of rules is minimal in the sense that if any one of these rules is removed, then circuits exist for which CSM cannot give correct test results. When all these rules are satisfied it can be formally shown that 1) all single irredundant BF’s can be detected by single vector tests and 2) a test vector that detects a single bridging fault fxalso detects all multiple BF’s that contain f1. To enhance the applicability of CSM, test and/or design strategies for dealing with circuits that do not satisfy each rule are proposed. Such circuits include a special exclusive or gate, BiCMOS circuits, domino logic, synchronous sequential circuits, and circuits implemented by the silicon on insulator (SOI) technology.

頁(從 - 到)659-670
期刊IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
出版狀態Published - 1992 五月

All Science Journal Classification (ASJC) codes

  • 軟體
  • 電腦繪圖與電腦輔助設計
  • 電氣與電子工程


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