Design for low-power, low-cost, and high-reliability precomputation-based content-addressable memory

C. S. Lin, J. C. Chang, B. D. Liu

研究成果: Conference contribution

10 引文 斯高帕斯(Scopus)

摘要

This paper presents a novel VLSI architecture for a fully parallel precomputation-based content addressable memory (PB-CAM) with low-power, low-cost, low-voltage, and high-reliability features. This design is based on a precomputation skill that saves not only power consumption of the PB-CAM system, but also reduces transistor count and operating voltage of the PB-CAM cell. In addition, the proposed CAM word structure adopts a static pseudo nMOS circuit design to improve system reliability. The whole design was fabricated with the TSMC 0.35 μm SPQM CMOS process parameters under 3.3 V supply voltage. With a 128 words by 30 bits CAM size, the measurement results indicate that the proposed circuit works up to 100 MHz with a power consumption of less than 33 mW. Furthermore, the low voltage measurement results show that the proposed circuit works up to 30 MHz under 1.5 V supply voltage.

原文English
主出版物標題Proceedings - APCCAS 2002
主出版物子標題Asia-Pacific Conference on Circuits and Systems
發行者Institute of Electrical and Electronics Engineers Inc.
頁面319-324
頁數6
ISBN(電子)0780376900
DOIs
出版狀態Published - 2002 一月 1
事件Asia-Pacific Conference on Circuits and Systems, APCCAS 2002 - Denpasar, Bali, Indonesia
持續時間: 2002 十月 282002 十月 31

出版系列

名字IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
2

Other

OtherAsia-Pacific Conference on Circuits and Systems, APCCAS 2002
國家Indonesia
城市Denpasar, Bali
期間02-10-2802-10-31

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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