Design in hot-carrier reliability for high performance logic applications

Peng Fang, Jiang Tao, Jone-Fang Chen, Chenming Hu

研究成果: Article同行評審

33 引文 斯高帕斯(Scopus)

摘要

Static (DC) and dynamic (AC) hot carrier degradation mechanisms were reviewed. Circuit performance degradation has been correlated to individual NMOS or PMOS device under DC stress. AC degradation model calibration and evaluation guidelines were also reviewed to ensure the use of hot-carrier reliability simulation tools in circuit level. As an example, thousand-hour inverter ring oscillator speed degradation data with different fanout, stress voltages, channel length, and processes are compared with that obtained from reliability simulation. The results show that reliability simulation is a powerful tool for logic circuit design optimization. It can predict the long-term circuit hot-carrier degradation accurately. The reliability of inverter, NAND, and NOR structures are also simulated and compared.

原文English
頁(從 - 到)525-531
頁數7
期刊Proceedings of the Custom Integrated Circuits Conference
出版狀態Published - 1998

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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