A physics-based study of floating-body effects on the operation of SOI DRAM is described. The study, which is based on device and circuit simulations using a physical SOI MOSFET model calibrated to an actual partially-depleted (PD) SOI DRAM technology, addresses the performance of the peripheral circuitry, e.g., the sense amplifier, as well as the dynamic retention of the data storage cell. Design insight for low-voltage high-density SOI DRAM is attained. Doable cell design is shown to yield dynamic retention time long enough for gigabit memories, and crude bodysource ties for nMOS, with pMOS bodies floating, are shown to effectively suppress instabilities in the sense amplifier.
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