Design issues and insights of multi-fin bulk silicon FinFETs

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

Multi-fin bulk silicon FinFET-based design issues and implications using 3D numerical simulation are presented for the first time. In order to gain sufficient drive current of each transistor, multi-fin layout is inevitable due to limited aspect ratio or fin height. However, how the multi-fin design impacts the circuit performance needs to be taken into account. Because of non-planar nature of the fin, conventional concept of multi-finger design in bulk CMOS technology does not apply. We found an extra leakage path underneath the fin spacing between source and drain. Such impact can be mitigated by additional substrate doping and proper gate-to-substrate isolation. Based on the proposed design window at a tight pitch control, good performance can be achieved while meeting leakage current requirement.

原文English
主出版物標題Proceedings of the 13th International Symposium on Quality Electronic Design, ISQED 2012
頁面723-726
頁數4
DOIs
出版狀態Published - 2012 七月 16
事件13th International Symposium on Quality Electronic Design, ISQED 2012 - Santa Clara, CA, United States
持續時間: 2012 三月 192012 三月 21

出版系列

名字Proceedings - International Symposium on Quality Electronic Design, ISQED
ISSN(列印)1948-3287
ISSN(電子)1948-3295

Other

Other13th International Symposium on Quality Electronic Design, ISQED 2012
國家/地區United States
城市Santa Clara, CA
期間12-03-1912-03-21

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程
  • 安全、風險、可靠性和品質

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