Design of 2D Systolic Array Accelerator for Quantized Convolutional Neural Networks

Chia Ning Liu, Yu An Lai, Chih Hung Kuo, Shi An Zhan

研究成果: Conference contribution

摘要

Quantization techniques have been studied to reduce the computing and memory requirement of deep neural networks. The full precision floating-point numbers are quantized into integer representation with lower bit-width. In this work, we quantize both activations and weights in CNN to 8-bit integers and apply our quantization method to the hardware accelerator. The accelerator is designed with a systolic-based structure, which can support both the convolutional layers and the fully-connected layers for various network models. By the proposed quantization scheme, there is only 1.68% mAP loss on YOLOv3-tiny model compared to the floating-point model. Benchmarked with AlexNet and VGG-16, the external memory access of convolutional layers is reduced by 1.63x and 1.79x compared with Eyeriss, and the internal memory access is also reduced by 7.31x and 17.48x.

原文English
主出版物標題2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781665419154
DOIs
出版狀態Published - 2021 四月 19
事件2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Hsinchu, Taiwan
持續時間: 2021 四月 192021 四月 22

出版系列

名字2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings

Conference

Conference2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021
國家/地區Taiwan
城市Hsinchu
期間21-04-1921-04-22

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 安全、風險、可靠性和品質
  • 儀器
  • 電氣與電子工程

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