Design of 60-GHz 90-nm CMOS balanced power amplifier with miniaturized quadrature hybrids

Chien Chih Lin, Chun Han Yu, Hsin Chih Kuo, Huey-Ru Chuang

研究成果: Conference contribution

6 引文 斯高帕斯(Scopus)

摘要

This paper presents a 60-GHz CMOS balanced power amplifier (PA) with miniaturized quadrature hybrids using 90-nm CMOS technology. To improve the output power and provide an area-efficient solution for the balanced PA design, a compact 3-dB quadrature hybrid constructed by a broadside-coupled scheme is employed as a low-insertion-loss power splitter/combiner. With a very short effective guided wavelength of 0.072 λg, the simulated insertion loss and phase difference of the quadrature hybrids are better than 0.5 dB and 90° ± 0.2°, respectively. The designed PA reaches a power gain exceeding 13.2 dB and a saturation power of 10.7 dBm with a power-added efficiency (PAE) more than 9 % at 60 GHz. The power consumption of the PA is 109 mW at a 1.2 V supply voltage. The chip size is 0.68 mm 2.

原文English
主出版物標題PAWR 2014 - Proceedings
主出版物子標題2014 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications
發行者IEEE Computer Society
頁面52-54
頁數3
ISBN(列印)9781479927784
DOIs
出版狀態Published - 2014 一月 1
事件2014 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications, PAWR 2014 - Newport Beach, CA, United States
持續時間: 2014 一月 192014 一月 22

出版系列

名字PAWR 2014 - Proceedings: 2014 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications

Other

Other2014 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications, PAWR 2014
國家/地區United States
城市Newport Beach, CA
期間14-01-1914-01-22

All Science Journal Classification (ASJC) codes

  • 電腦網路與通信

指紋

深入研究「Design of 60-GHz 90-nm CMOS balanced power amplifier with miniaturized quadrature hybrids」主題。共同形成了獨特的指紋。

引用此