Design of 60-GHz compact and low-insertion loss stepped-impedance coupled-line CMOS on-chip bandpass filter

Po Kai Chuang, Lung Kai Yeh, Huey Ru Chuang

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

This paper presents the design and implementation of a 60-GHz compact and low-insertion loss on-chip bandpass filter (BPF) with using a 0.18-μm standard CMOS process. For size reduction, the symmetric short-ended parallel coupled line with cascaded transmission lines is loaded with open-ended two-section stepped-impedance (SI) transmission lines. The final layout structure can be further miniaturized by properly folding the resonators. The measured results show that the fabricated BPF exhibits an insertion loss less than 3 dB and a return loss better than 16 dB. Considering the trade-off between the insertion loss and the band-edge cutoff rate, the transmission zero designed by the SI transmission lines is located at 80 GHz. The chip core size is 0.23 × 0.31 mm2 (0.09 × 0.12 λg2).

原文English
主出版物標題2014 Asia-Pacific Microwave Conference Proceedings, APMC 2014
發行者Institute of Electrical and Electronics Engineers Inc.
頁面1232-1234
頁數3
ISBN(電子)9784902339314
出版狀態Published - 2014 三月 25
事件2014 Asia-Pacific Microwave Conference, APMC 2014 - Sendai, Japan
持續時間: 2014 十一月 42014 十一月 7

出版系列

名字2014 Asia-Pacific Microwave Conference Proceedings, APMC 2014

Other

Other2014 Asia-Pacific Microwave Conference, APMC 2014
國家/地區Japan
城市Sendai
期間14-11-0414-11-07

All Science Journal Classification (ASJC) codes

  • 電腦網路與通信
  • 硬體和架構
  • 電氣與電子工程

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