摘要
This article presents the design, implementation and measurement of a 5.7 GHz CMOS LNA for an IEEE 802.11a WLAN receiver. The LNA, fabricated with the 0.18μm 1P6M standard CMOS process, uses a current-reuse technology to increase linear gain and save power consumption. The circuit measurements are performed using an FR-4 PCB test fixture. The fabricated LNA exhibits a linear gain of 11.2 dB, a noise figure of 4.5 dB and an input P1dB of -10 dBm at 5.8 GHz. The power consumption is 14.4 mW at V DD = 1.8 V.
原文 | English |
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頁面 | 132-136 |
頁數 | 5 |
卷 | 47 |
無 | 2 |
專業出版物 | Microwave Journal |
出版狀態 | Published - 2004 2月 1 |
All Science Journal Classification (ASJC) codes
- 電氣與電子工程