Design of a giga-bit hardware accelerator for the iSCSI initiator

Chung-Ho Chen, Yi Cheng Chung, Chen Hua Wang, Han Chiang Chen

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

摘要

We present the design of an iSCSI hardware accelerator for the initiator subsystem of a host bus adapter (iSCSI HBA). By analyzing the UNH-iSCSI open source code, first we evaluate the software performance and present a general methodology that transforms the software C code into the hardware HDL implementation. For the hardware module, the datapath design maximizes the concurrent accesses achievable within a clock cycle by using a dual-port descriptor memory. The synthesizable iSCSI hardware accelerator achieves 100 MHz speed and costs about 85K gates in the 0.18u technology. The design is able to meet the requirement of 1Gbps network when the average iSCSI PDU size is greater than 125 bytes.

原文English
主出版物標題Proceedings - The 31st IEEE Conference on Local Computer Networks, LCN 2006
頁面257-263
頁數7
DOIs
出版狀態Published - 2006 十二月 1
事件31st Annual IEEE Conference on Local Computer Networks, LCN 2006 - Tampa, FL, United States
持續時間: 2006 十一月 142006 十一月 16

出版系列

名字Proceedings - Conference on Local Computer Networks, LCN

Other

Other31st Annual IEEE Conference on Local Computer Networks, LCN 2006
國家/地區United States
城市Tampa, FL
期間06-11-1406-11-16

All Science Journal Classification (ASJC) codes

  • 工程 (全部)

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