Given a binary number N, the simplest way for evaluating its square N 2 is the use of ROM look-up tables. For example, the squares of 12-bit numbers can be stored in a ROM of (2 12 × 24) bits, which takes an area of 3.5mm 2 and an access time of 9.96ns with 0.8μm CMOS process. However, the conventional ROM-table approaches are limited only for small bit-size applications due to the unmanageable increase of the ROM table size. In this paper, a novel design of square generator circuit using a folding approach is presented for high-speed performance applications. Results show that, with the same process, the proposed square generator circuit takes 12.27ns to generate the squares of 40-bit numbers with an area of about 2.88 times that of the (2 12 × 24)-ROM, i.e., 10mm 2. There exists a design trade-off between speed and area. A nested structure is also presented to achieve a 103-bit square generator with a delay of 15.82ns. The bit size can be further increased by adding more levels of the nested structure. The results are promising and thus the proposed approach is well suitable for large bit-size and high-speed applications.
All Science Journal Classification (ASJC) codes
- Theoretical Computer Science
- Hardware and Architecture
- Computational Theory and Mathematics