Design of a Low-Jitter 5.4 Gbps Half-Rate Clock and Data Recovery Circuit for eDP Application

This paper demonstrates a 5.4 Gb/s half-rate dual-loop clock and data recovery (CDR) circuit, which is designated to support the specifications of Embedded DisplayPort (eDP) 1.2 High Bit Rate 2 Mode (HBR2). The proposed reference-less CDR raised several key techniques: a dual-loop architecture constructed by a phase-locked loop (PLL) and a frequencylocked loop (FLL), an accurate lock detector is adopted to minimize interference between PLL and FLL while reducing power consumption, a digital low-power and low-charge injection up/down combiner can prevent the usage of multiple charge pumps, a delay-based frequency detector requires no complex multiphase clock generator, and a charge pump achieves less charge injections through a dummy MOS capacitor. The proposed CDR was implemented using 40 nm CMOS technology, and can achieve a 1.9 ps rms data jitter and a 1.61 ps rms clock jitter while dissipating 19.7 mW.