Design of a pipelined and expandable sorting architecture with simple control scheme

This paper presents a novel circuit for the pipelined and expandable sorting architecture that processes thirty-two 16-bit patterns at a time. This design is based on a compare-swap cell which can easily be cascaded to improve our sorting performance. The sorting architecture combines suitable algorithm to sort arbitrary N data patterns. The proposed hardware architecture features layout regularity and interconnection compactness, thus it can be exploited to obtain a small and efficient hardware implementation. The whole design was fabricated by TSMC 0.35μm SPQM CMOS process. The estimation results indicate that the sorter can work up to 66MHz with the power consumption less than 20mW under 3.3V supply voltage. This design is suitable for VLSI implementation. It can also be applied well when being embedded in digital signal processors.