Design of a shared buffer management scheme for ATM switches

C. S. Lin, B. D. Liu, Y. C. Tane

研究成果: Conference contribution

3 引文 斯高帕斯(Scopus)

摘要

This paper presents a novel memory management scheme for shared buffer ATM switch that features low cost, high throughput, and high memory utilization. The design approach is based on the dual-port RAM device which can improve the memory bandwidth and reduce the complex address control of shared buffer. In addition, the proposed memory management scheme adopts a temporary-point approach to improve the conventional bubble elimination design. The temporary-point approach eliminates the bubble problem of linked list chain, as well as achieves double throughput performance compared with conventional single-port RAM shared buffer architecture, The whole design was fabricated with the TSMC 0.35 μm SPQM CMOS process parameters under 3.3 V supply voltage. With a 256 cells shared buffer architecture, the measured results show that both cell-writing process and cell-reading process of this chip worked in parallel with the speed up to 25 MHz.

原文English
主出版物標題Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
編輯John Chickanosky, Ram K. Krishnamurthy, P.R. Mukund
發行者Institute of Electrical and Electronics Engineers Inc.
頁面261-264
頁數4
ISBN(電子)0780374940
DOIs
出版狀態Published - 2002 一月 1
事件15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States
持續時間: 2002 九月 252002 九月 28

出版系列

名字Proceedings of the Annual IEEE International ASIC Conference and Exhibit
2002-January
ISSN(列印)1063-0988

Other

Other15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
國家/地區United States
城市Rochester
期間02-09-2502-09-28

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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