Design of AND and NAND logic gate using NDR-based circuit suitable for CMOS process

Dong Shong Liang, Cheng-Chi Tai, Kwang Jow Gan, Cher Shiung Tsai, Yaw Hwang Chen

研究成果: Conference contribution

3 引文 斯高帕斯(Scopus)

摘要

AND and NAND logic gate based on the negative differential resistance (NDR) device is demonstrated. This NDR device is made of metal-oxide-semiconductor field-effect-transistor (MOS) devices that could exhibit the NDR characteristic in the current-voltage curve by suitably arranging the MOS parameters. The devices and circuits are implemented by the standard 0.35μm CMOS process.

原文English
主出版物標題APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
頁面1325-1328
頁數4
DOIs
出版狀態Published - 2006 十二月 1
事件APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - , Singapore
持續時間: 2006 十二月 42006 十二月 6

出版系列

名字IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

OtherAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
國家/地區Singapore
期間06-12-0406-12-06

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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