A design technique for current-mode square-root domain band-pass filter fabricated in a 0.25 μ m CMOS process is presented. The basic building block consists of current-mode current mirrors, square-root circuits and capacitors, and in which the overall supply voltage is reduced by adopting low-voltage level-shift current mirror. Both of the simulation and measured results, which are in good agreement, indicate that the prototype of the band-pass provides tunable center frequency of 4-10 MHz with bias-current-tunable, -26.7 dB total harmonic distortion (THD), and approximately 1.598 mW power dissipation with a 1.5 V supply voltage. Advantages of the proposed filter include high frequency operation, tuneability, low supply voltage operation, low power consumption, and low third order intermodulation distortion.
All Science Journal Classification (ASJC) codes