A design-for-testability approach based on die M-testability conditions is applied to the bit-level VLSI systolic arrays for discrete cosine transform (DCT). Our M-testability conditions guarantee 100% single-cellfault testability with a minimum number of test patterns. A hardware overhead of no more than 6% is sufficient to make the DCT arrays M-testable. The resulting number of test patterns is only 16, regardless of the size of the DCT array and the internal word length. Apart from the cell-fault model, we also discuss the DCT array testing using die module-fault model. This method detects all possible combinational module faults pseudoexhaustively. Since practical DCT arrays can be quite large, diagnosis for the array is considered important. We propose an off-line fault diagnosis scheme which detects and locates any faulty module by a self-comparison approach.