Design of easily testable VLSI arrays for discrete cosine transform

Shyue Kung Lu, Cheng Wen Wu, Sy Yen Kuo

研究成果: Conference contribution

3 引文 斯高帕斯(Scopus)

摘要

A design-for-testability approach based on die M-testability conditions is applied to the bit-level VLSI systolic arrays for discrete cosine transform (DCT). Our M-testability conditions guarantee 100% single-cellfault testability with a minimum number of test patterns. A hardware overhead of no more than 6% is sufficient to make the DCT arrays M-testable. The resulting number of test patterns is only 16, regardless of the size of the DCT array and the internal word length. Apart from the cell-fault model, we also discuss the DCT array testing using die module-fault model. This method detects all possible combinational module faults pseudoexhaustively. Since practical DCT arrays can be quite large, diagnosis for the array is considered important. We propose an off-line fault diagnosis scheme which detects and locates any faulty module by a self-comparison approach.

原文English
主出版物標題Conference Record of the 26th Asilomar Conference on Signals, Systems and Computers, ACSSC 1992
發行者IEEE Computer Society
頁面989-993
頁數5
ISBN(電子)0818631600
DOIs
出版狀態Published - 1992 一月 1
事件26th Asilomar Conference on Signals, Systems and Computers, ACSSC 1992 - Pacific Grove, United States
持續時間: 1992 十月 261992 十月 28

出版系列

名字Conference Record - Asilomar Conference on Signals, Systems and Computers
ISSN(列印)1058-6393

Conference

Conference26th Asilomar Conference on Signals, Systems and Computers, ACSSC 1992
國家/地區United States
城市Pacific Grove
期間92-10-2692-10-28

All Science Journal Classification (ASJC) codes

  • 訊號處理
  • 電腦網路與通信

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