Design of fault-tolerance on Boolean n-cube architectures

Chu Sing Yang, Shun Yue Wu

研究成果: Article同行評審

摘要

The goal of the paper is to design Boolean n-cube architectures that can tolerate node (processor) failures, called fault-tolerant Boolean n-cubes. While a number of such fault-tolerant Boolean n-cube designs have been previously proposed, most of these designs usually require large hardware overhead, which may be not practical in many applications. In this paper, we present a new approach to the design of fault-tolerant Boolean n-cubes that can achieve the same reliability as some previous schemes while requiring less hardware overhead. We first build a fault-tolerant module containing 2m original nodes with k spare nodes, and then construct the fault-tolerant Boolean n-cube by using a number of such modules. In each module, every spare node can replace any other original or spare node failure. Hence, full spare utilization is achieved in each module. Furthermore, the proposed reconfiguration procedure can be done simply and quickly; i.e., only short time overhead is required during reconfiguration.

原文English
頁(從 - 到)298-304
頁數7
期刊Proceedings of the National Science Council, Republic of China, Part A: Physical Science and Engineering
18
發行號3
出版狀態Published - 1994 五月 1

All Science Journal Classification (ASJC) codes

  • 工程 (全部)

指紋

深入研究「Design of fault-tolerance on Boolean n-cube architectures」主題。共同形成了獨特的指紋。

引用此