Design of gate-all-around silicon mosfets for 6-T Sram area efficiency and yield

Yi Bo Liao, Meng-Hsueh Chiang, Nattapol Damrongplasit, Wei-Chou Hsu, Tsu Jae King Liu

研究成果: Article

10 引文 (Scopus)

摘要

Gate-all-around (GAA) MOSFETs relevant for the 11.9-nm CMOS technology node are optimized with device dimensions following the scale length rule. Variability in transistor performance due to systematic and random variations is estimated with the aid of TCAD 3-D device simulations, for these well-tempered GAA structures. The tradeoff between read stability and write-ability of 6-T static RAM cell designs implemented with GAA MOSFETs with either square or rectangular nanowire channel regions is then investigated, and a calibrated transistor I-V compact model is used to estimate cell yield. The results indicate that a rectangular (thin and wide) channel design achieves the optimal balance between the read yield and write yield and hence provides for the lowest minimum cell operating voltage, estimated to be ~0.45 V, as well as smaller cell area.

原文English
文章編號6823112
頁(從 - 到)2371-2377
頁數7
期刊IEEE Transactions on Electron Devices
61
發行號7
DOIs
出版狀態Published - 2014 一月 1

指紋

Silicon
Transistors
Random access storage
Nanowires
Electric potential
thiazole-4-carboxamide adenine dinucleotide

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

引用此文

Liao, Yi Bo ; Chiang, Meng-Hsueh ; Damrongplasit, Nattapol ; Hsu, Wei-Chou ; Liu, Tsu Jae King. / Design of gate-all-around silicon mosfets for 6-T Sram area efficiency and yield. 於: IEEE Transactions on Electron Devices. 2014 ; 卷 61, 編號 7. 頁 2371-2377.
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Design of gate-all-around silicon mosfets for 6-T Sram area efficiency and yield. / Liao, Yi Bo; Chiang, Meng-Hsueh; Damrongplasit, Nattapol; Hsu, Wei-Chou; Liu, Tsu Jae King.

於: IEEE Transactions on Electron Devices, 卷 61, 編號 7, 6823112, 01.01.2014, p. 2371-2377.

研究成果: Article

TY - JOUR

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AU - Hsu, Wei-Chou

AU - Liu, Tsu Jae King

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