Design of high-resolution pipelined analog-to-digital converters using Multiple-Phase Capacitor-Splitting feedback interchange technique

Chih Haur Huang; Soon Jyh Chang; Kuen Jong Lee

Design of high-resolution pipelined analog-to-digital converters using Multiple-Phase Capacitor-Splitting feedback interchange technique

Chih Haur Huang, Soon Jyh Chang, Kuen Jong Lee

電機工程學系

研究成果: Paper › 同行評審

1 引文斯高帕斯（Scopus）

摘要

In this paper, a new technique, the Multiple-Phase Capacitor-Splitting Feedback Interchange (MP-CSFI) technique, is presented to reduce the harmonic distortion due to capacitor mismatch for pipelined ADCs. The basic idea is to split the capacitors in the sub-DACs of a pipelined ADC and dynamically select subsets of the split capacitors as the feedback ones during its operation such that the non-ideal effects caused by capacitors' mismatches can be disturbed and modulated to higher frequency band. A 12-bit, 35MHz pipelined A/D converter with the proposed technique is designed and simulated using the TSMC 0.25 μm 1P5M technology to demonstrate the effectiveness of this technique.

原文	English
頁面	625-628
頁數	4
出版狀態	Published - 2004 12月 1
事件	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan 持續時間: 2004 12月 6 → 2004 12月 9

Other

Other	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
國家/地區	Taiwan
城市	Tainan
期間	04-12-06 → 04-12-09

All Science Journal Classification (ASJC) codes

電氣與電子工程

其它文件與鏈接

引用此

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title = "Design of high-resolution pipelined analog-to-digital converters using Multiple-Phase Capacitor-Splitting feedback interchange technique",

abstract = "In this paper, a new technique, the Multiple-Phase Capacitor-Splitting Feedback Interchange (MP-CSFI) technique, is presented to reduce the harmonic distortion due to capacitor mismatch for pipelined ADCs. The basic idea is to split the capacitors in the sub-DACs of a pipelined ADC and dynamically select subsets of the split capacitors as the feedback ones during its operation such that the non-ideal effects caused by capacitors' mismatches can be disturbed and modulated to higher frequency band. A 12-bit, 35MHz pipelined A/D converter with the proposed technique is designed and simulated using the TSMC 0.25 μm 1P5M technology to demonstrate the effectiveness of this technique.",

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year = "2004",

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Design of high-resolution pipelined analog-to-digital converters using Multiple-Phase Capacitor-Splitting feedback interchange technique. / Huang, Chih Haur; Chang, Soon Jyh ; Lee, Kuen Jong.
2004. 625-628 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.

研究成果: Paper › 同行評審

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AU - Lee, Kuen Jong

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N2 - In this paper, a new technique, the Multiple-Phase Capacitor-Splitting Feedback Interchange (MP-CSFI) technique, is presented to reduce the harmonic distortion due to capacitor mismatch for pipelined ADCs. The basic idea is to split the capacitors in the sub-DACs of a pipelined ADC and dynamically select subsets of the split capacitors as the feedback ones during its operation such that the non-ideal effects caused by capacitors' mismatches can be disturbed and modulated to higher frequency band. A 12-bit, 35MHz pipelined A/D converter with the proposed technique is designed and simulated using the TSMC 0.25 μm 1P5M technology to demonstrate the effectiveness of this technique.

AB - In this paper, a new technique, the Multiple-Phase Capacitor-Splitting Feedback Interchange (MP-CSFI) technique, is presented to reduce the harmonic distortion due to capacitor mismatch for pipelined ADCs. The basic idea is to split the capacitors in the sub-DACs of a pipelined ADC and dynamically select subsets of the split capacitors as the feedback ones during its operation such that the non-ideal effects caused by capacitors' mismatches can be disturbed and modulated to higher frequency band. A 12-bit, 35MHz pipelined A/D converter with the proposed technique is designed and simulated using the TSMC 0.25 μm 1P5M technology to demonstrate the effectiveness of this technique.

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Design of high-resolution pipelined analog-to-digital converters using Multiple-Phase Capacitor-Splitting feedback interchange technique

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All Science Journal Classification (ASJC) codes

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