Design of high-resolution pipelined analog-to-digital converters using Multiple-Phase Capacitor-Splitting feedback interchange technique

Chih Haur Huang, Soon Jyh Chang, Kuen Jong Lee

研究成果: Paper

1 引文 (Scopus)

摘要

In this paper, a new technique, the Multiple-Phase Capacitor-Splitting Feedback Interchange (MP-CSFI) technique, is presented to reduce the harmonic distortion due to capacitor mismatch for pipelined ADCs. The basic idea is to split the capacitors in the sub-DACs of a pipelined ADC and dynamically select subsets of the split capacitors as the feedback ones during its operation such that the non-ideal effects caused by capacitors' mismatches can be disturbed and modulated to higher frequency band. A 12-bit, 35MHz pipelined A/D converter with the proposed technique is designed and simulated using the TSMC 0.25 μm 1P5M technology to demonstrate the effectiveness of this technique.

原文English
頁面625-628
頁數4
出版狀態Published - 2004 十二月 1
事件2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
持續時間: 2004 十二月 62004 十二月 9

Other

Other2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
國家Taiwan
城市Tainan
期間04-12-0604-12-09

指紋

Interchanges
Digital to analog conversion
Capacitors
Feedback
Harmonic distortion
Frequency bands

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

引用此文

Huang, C. H., Chang, S. J., & Lee, K. J. (2004). Design of high-resolution pipelined analog-to-digital converters using Multiple-Phase Capacitor-Splitting feedback interchange technique. 625-628. 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.
Huang, Chih Haur ; Chang, Soon Jyh ; Lee, Kuen Jong. / Design of high-resolution pipelined analog-to-digital converters using Multiple-Phase Capacitor-Splitting feedback interchange technique. 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.4 p.
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Huang, CH, Chang, SJ & Lee, KJ 2004, 'Design of high-resolution pipelined analog-to-digital converters using Multiple-Phase Capacitor-Splitting feedback interchange technique', 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan, 04-12-06 - 04-12-09 頁 625-628.

Design of high-resolution pipelined analog-to-digital converters using Multiple-Phase Capacitor-Splitting feedback interchange technique. / Huang, Chih Haur; Chang, Soon Jyh; Lee, Kuen Jong.

2004. 625-628 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.

研究成果: Paper

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N2 - In this paper, a new technique, the Multiple-Phase Capacitor-Splitting Feedback Interchange (MP-CSFI) technique, is presented to reduce the harmonic distortion due to capacitor mismatch for pipelined ADCs. The basic idea is to split the capacitors in the sub-DACs of a pipelined ADC and dynamically select subsets of the split capacitors as the feedback ones during its operation such that the non-ideal effects caused by capacitors' mismatches can be disturbed and modulated to higher frequency band. A 12-bit, 35MHz pipelined A/D converter with the proposed technique is designed and simulated using the TSMC 0.25 μm 1P5M technology to demonstrate the effectiveness of this technique.

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Huang CH, Chang SJ, Lee KJ. Design of high-resolution pipelined analog-to-digital converters using Multiple-Phase Capacitor-Splitting feedback interchange technique. 2004. 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.