Design of high-speed bit-serial divider in GF(2m)

Wen Ching Lin, Ming-Der Shieh, Chien Ming Wu

研究成果: Conference contribution

3 引文 斯高帕斯(Scopus)

摘要

In this paper, we reformulated the conventional iterative division algorithm by substituting the pre-defined variable and then updating its initial value accordingly. The reformulated division algorithm allows a restructuring of the divider architecture to further improve its operating speed without increasing latency and area cost. Using the proposed fast algorithm, we developed a high-speed bit-serial GF(2m) divider. Analytical results show that the cost of the initial value update and variable transformation in the reformulated algorithm is almost negligible in the hardware implementation. Our divider reduces the critical path delay. Compared with related divider designs, the proposed design has time and area advantages.

原文English
主出版物標題ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
主出版物子標題Nano-Bio Circuit Fabrics and Systems
頁面713-716
頁數4
DOIs
出版狀態Published - 2010 八月 31
事件2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France
持續時間: 2010 五月 302010 六月 2

出版系列

名字ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Other

Other2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
國家/地區France
城市Paris
期間10-05-3010-06-02

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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