Design of high-speed iterative dividers in GF(2m)

Ming Der Shieh, Wen Ching Lin, Chien Ming Wu

研究成果: Article同行評審

摘要

Fast algorithms for high-speed divider design in finite fields GF(2 m) are very crucial in applications like cryptosystems. In this paper, we reformulated the conventional iterative division algorithm by changing the pre-defined variable and then updating its initial value accordingly. The reformulated division algorithm allows a restructuring of the divider architecture to further improve its operating speed without increasing latency or area cost. Using the proposed fast algorithm, we developed two high-speed iterative dividers based on the semi-systolic and bit-serial systolic architectures. Analytical results show that the cost of the initial value update and variable transformation in the reformulated algorithm is almost negligible in the hardware implementation. Our divider designs improve the critical path delay. Compared with related divider designs, the proposed designs have time and area advantages.

原文English
頁(從 - 到)953-967
頁數15
期刊Journal of Information Science and Engineering
27
發行號3
出版狀態Published - 2011 五月 1

All Science Journal Classification (ASJC) codes

  • 軟體
  • 人機介面
  • 硬體和架構
  • 圖書館與資訊科學
  • 計算機理論與數學

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