Design of low-error fixed-width multiplier for DSP applications

Jer Min Jou, Shiann Rong Kuang

研究成果: Article同行評審

17 引文 斯高帕斯(Scopus)

摘要

A low-error design of the fixed-width parallel multiplier for digital signal processing (DSP) applications is proposed. Applying two n bit inputs, it generates the n bit, instead of 2n bit, product with lower relative product errors, but uses only about half the area of a standard parallel multiplier. These features make it very suitable for use in many DSP applications such as arithmetic coding, wavelet transformation, digital filtering.

原文English
頁(從 - 到)1597-1598
頁數2
期刊Electronics Letters
33
發行號19
DOIs
出版狀態Published - 1997 九月 11

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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