Design of pipelined mixed-signal fuzzy logic controller with linguistic hedge modifiers

Chuen Yau Chen; Yuan Ta Hsieh; Bin Da Liu

Design of pipelined mixed-signal fuzzy logic controller with linguistic hedge modifiers

Chuen Yau Chen, Yuan Ta Hsieh, Bin Da Liu

電機工程學系

研究成果: Paper › 同行評審

摘要

In this paper, we realize the linguistic hedge fuzzy logic controller in a mixed-signal VLSI design with pipelined clocking strategy. Current-mode approach is adopted in designing the signal processing portions to simplify the circuit complexity; digital circuits are adopted to implement the programmable units. All the designs are performed with HSPICE simulation in level 28 model for a 0.35μm SPQM CMOS process. The pipelined strategy speeds up the inference operation to 0.5M FLIPS. The supply voltage of this system is 3.3V.

原文	English
頁面	148-151
頁數	4
出版狀態	Published - 2000
事件	2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems - Tianjin, China 持續時間: 2000 12月 4 → 2000 12月 6

Other

Other	2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems
國家/地區	China
城市	Tianjin
期間	00-12-04 → 00-12-06

All Science Journal Classification (ASJC) codes

電氣與電子工程

其它文件與鏈接

引用此

@conference{ef26002824044c82b959f518ed3e6269,

title = "Design of pipelined mixed-signal fuzzy logic controller with linguistic hedge modifiers",

abstract = "In this paper, we realize the linguistic hedge fuzzy logic controller in a mixed-signal VLSI design with pipelined clocking strategy. Current-mode approach is adopted in designing the signal processing portions to simplify the circuit complexity; digital circuits are adopted to implement the programmable units. All the designs are performed with HSPICE simulation in level 28 model for a 0.35μm SPQM CMOS process. The pipelined strategy speeds up the inference operation to 0.5M FLIPS. The supply voltage of this system is 3.3V.",

author = "Chen, {Chuen Yau} and Hsieh, {Yuan Ta} and Liu, {Bin Da}",

year = "2000",

language = "English",

pages = "148--151",

note = "2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems ; Conference date: 04-12-2000 Through 06-12-2000",

}

TY - CONF

T1 - Design of pipelined mixed-signal fuzzy logic controller with linguistic hedge modifiers

AU - Chen, Chuen Yau

AU - Hsieh, Yuan Ta

AU - Liu, Bin Da

PY - 2000

Y1 - 2000

N2 - In this paper, we realize the linguistic hedge fuzzy logic controller in a mixed-signal VLSI design with pipelined clocking strategy. Current-mode approach is adopted in designing the signal processing portions to simplify the circuit complexity; digital circuits are adopted to implement the programmable units. All the designs are performed with HSPICE simulation in level 28 model for a 0.35μm SPQM CMOS process. The pipelined strategy speeds up the inference operation to 0.5M FLIPS. The supply voltage of this system is 3.3V.

AB - In this paper, we realize the linguistic hedge fuzzy logic controller in a mixed-signal VLSI design with pipelined clocking strategy. Current-mode approach is adopted in designing the signal processing portions to simplify the circuit complexity; digital circuits are adopted to implement the programmable units. All the designs are performed with HSPICE simulation in level 28 model for a 0.35μm SPQM CMOS process. The pipelined strategy speeds up the inference operation to 0.5M FLIPS. The supply voltage of this system is 3.3V.

UR - http://www.scopus.com/inward/record.url?scp=2342634483&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=2342634483&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:2342634483

SP - 148

EP - 151

T2 - 2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems

Y2 - 4 December 2000 through 6 December 2000

ER -

Design of pipelined mixed-signal fuzzy logic controller with linguistic hedge modifiers

摘要

Other

All Science Journal Classification (ASJC) codes

其它文件與鏈接

指紋

引用此