Design of UWB RF receiver front-end with heterogeneous chip integration

Y. C. Lin, R. F. Ye, C. T. Lee, T. S. Horng, L. T. Hwang, J. M. Wu

研究成果: Conference contribution

7 引文 斯高帕斯(Scopus)


In this work, a 3-5 GHz CMOS UWB RF receiver front-end design is described. The design was realized using integrated passive device (IPD) package format as system-in-package (SiP) application. The CMOS circuit consists of a fully differential common gate-low noise amplifier (CG-LNA), an IQ downconversion mixer, and a variable gain amplifier. Three low loss IPD transformer baluns are used to convert unbalanced signals into balanced signals for feeding into the RF and LO input ports of the CMOS circuit. Measurement results indicate that the average conversion gain is 16.3 dB while the average IIP3 and noise figure are around 10.4 dBm and 6.1 dB, respectively, over the entire operating frequency range.

主出版物標題Asia-Pacific Microwave Conference Proceedings, APMC 2011
出版狀態Published - 2011 十二月 1
事件Asia-Pacific Microwave Conference, APMC 2011 - Melbourne, VIC, Australia
持續時間: 2011 十二月 52011 十二月 8


名字Asia-Pacific Microwave Conference Proceedings, APMC


OtherAsia-Pacific Microwave Conference, APMC 2011
城市Melbourne, VIC

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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