Design optimization for wafer level package reliability by using artificial neural network

P. C. Lai, Tz-Cheng Chiu, G. S. Shen

研究成果: Conference contribution

3 引文 斯高帕斯(Scopus)

摘要

An artificial neural network (ANN) based multi-objective design optimization for a wafer level package (WLP) is presented. Design factors including bump pad configuration, solder alloy composition, bump pad opening diameter, pad overhang (Cu pad radius minus pad opening radius), redistribution layer (RDL) polymer dielectric thickness and under-bump Cu thickness are grouped and considered by using a 3-level full factorial design of simulations (DoS) procedure. Key failure indices corresponding to solder joint fatigue fracture, RDL trace fatigue fracture and polymer dielectric cracking are selected as the objective functions for the design optimization. The Pareto optimal solutions are determined by using a genetic algorithm, and the compromise programming method is applied to determine the most reliable design.

原文English
主出版物標題2013 8th International Microsystems, Packaging, Assembly and Circuits Technology Conference - Green and Cloud
主出版物子標題Creating Value and Toward Eco-Life, IMPACT 2013 - Proceedings
頁面172-175
頁數4
DOIs
出版狀態Published - 2013 十二月 1
事件2013 8th International Microsystems, Packaging, Assembly and Circuits Technology Conference - Green and Cloud: Creating Value and Toward Eco-Life, IMPACT 2013 - Taipei, Taiwan
持續時間: 2013 十月 222013 十月 25

出版系列

名字Proceedings of Technical Papers - International Microsystems, Packaging, Assembly, and Circuits Technology Conference, IMPACT
ISSN(列印)2150-5934
ISSN(電子)2150-5942

Other

Other2013 8th International Microsystems, Packaging, Assembly and Circuits Technology Conference - Green and Cloud: Creating Value and Toward Eco-Life, IMPACT 2013
國家/地區Taiwan
城市Taipei
期間13-10-2213-10-25

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 控制與系統工程
  • 電氣與電子工程

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