Design optimization in write speed of multi-level cell application for phase change memory

Jun Tin Lin, Yi Bo Liao, Meng Hsueh Chiang, I. Hsuan Chiu, Chia Long Lin, Wei Chou Hsu, Pei Chia Chiang, Shyh Shyuan Sheu, Yen Ya Hsu, Wen Hsing Liu, Keng Li Su, Ming Jer Kao, Ming Jinn Tsai

研究成果: Conference contribution

11 引文 斯高帕斯(Scopus)

摘要

Design optimization to improve write speed of phase change memory is shown achievable by using a physical yet analytical compact PCM model. Our simulation results suggested that the write speed of continuous pulse programming scheme can be optimized and is superior to slow quenching scheme for multi-level cell application.

原文English
主出版物標題2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009
頁面525-528
頁數4
DOIs
出版狀態Published - 2009 十二月 1
事件2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009 - Xi'an, China
持續時間: 2009 十二月 252009 十二月 27

出版系列

名字2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009

Other

Other2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009
國家/地區China
城市Xi'an
期間09-12-2509-12-27

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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