DfT architecture for 3D-SICs with multiple towers

Chun Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng Wen Wu

研究成果: Conference contribution

30 引文 斯高帕斯(Scopus)

摘要

Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) provide attractive benefits such as smaller form factor, higher performance, and lower power. So far, prior work on Design-for-Testability (DfT) only focused on 3D-SICs consisting of a single "tower", i.e., a 3D-SIC in which each stack level contains exactly one die. 3D stacking technology allows to place multiple dies on top of a common base die, resulting in 3D-SICs with multiple "towers". This paper presents a generic DfT architecture for 3D-SICs having any number of "towers", possibly including "sub-towers". We also present efficient test control mechanisms. Experimental results show that the proposed architecture has a negligible area cost for medium-sized and larger industrial designs, and therefore provides a cost-effective test solution for 3D-SICs.

原文English
主出版物標題Proceedings - 16th IEEE European Test Symposium, ETS 2011
頁面51-56
頁數6
DOIs
出版狀態Published - 2011 八月 29
事件16th IEEE European Test Symposium, ETS 2011 - Trondheim, Norway
持續時間: 2011 五月 232011 五月 27

出版系列

名字Proceedings - 16th IEEE European Test Symposium, ETS 2011

Conference

Conference16th IEEE European Test Symposium, ETS 2011
國家Norway
城市Trondheim
期間11-05-2311-05-27

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

指紋 深入研究「DfT architecture for 3D-SICs with multiple towers」主題。共同形成了獨特的指紋。

引用此