Diagnostic fault simulation for synchronous sequential circuits

Shung Chih Chen, Jer-Min Jou

研究成果: Article

4 引文 (Scopus)

摘要

In this paper, a time and memory-efficient diagnostic fault simulator for sequential circuits is first presented. A distributed diagnostic fault simulator is then presented based on the sequential algorithm to improve the speed of the diagnostic process. In the sequential diagnostic fault simulator, the number of fault-pair output response comparisons has been minimized by using an indistinguishability fault list that stores the faults that are indistinguishable from each fault. Due to the symmetrical relationship of the fault-pair distinguishability, fault list sizes are reduced. Therefore, the different diagnostic measures of a given test set can be generated very quickly using a small amount of memory. To further speed up the process of finding the indistinguishable fault list for each fault, a distributed approach is proposed and developed. The major idea for this approach is that each processor constructs the indistinguishable fault lists for a certain percentage of faults only. Experimental results show that the sequential diagnostic fault simulator runs faster and uses less memory than a previously developed one and that the distributed algorithm even achieves superlinear speedup for a very large sequential benchmark circuit, s35932. To the authors' knowledge, no distributed diagnostic fault simulation system for sequential circuits has been proposed before.

原文English
頁(從 - 到)299-308
頁數10
期刊IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
16
發行號3
DOIs
出版狀態Published - 1997 十二月 1

指紋

Sequential circuits
Simulators
Data storage equipment
Parallel algorithms

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

引用此文

@article{dd9f4a6dedd341aeb5ef736cd2712908,
title = "Diagnostic fault simulation for synchronous sequential circuits",
abstract = "In this paper, a time and memory-efficient diagnostic fault simulator for sequential circuits is first presented. A distributed diagnostic fault simulator is then presented based on the sequential algorithm to improve the speed of the diagnostic process. In the sequential diagnostic fault simulator, the number of fault-pair output response comparisons has been minimized by using an indistinguishability fault list that stores the faults that are indistinguishable from each fault. Due to the symmetrical relationship of the fault-pair distinguishability, fault list sizes are reduced. Therefore, the different diagnostic measures of a given test set can be generated very quickly using a small amount of memory. To further speed up the process of finding the indistinguishable fault list for each fault, a distributed approach is proposed and developed. The major idea for this approach is that each processor constructs the indistinguishable fault lists for a certain percentage of faults only. Experimental results show that the sequential diagnostic fault simulator runs faster and uses less memory than a previously developed one and that the distributed algorithm even achieves superlinear speedup for a very large sequential benchmark circuit, s35932. To the authors' knowledge, no distributed diagnostic fault simulation system for sequential circuits has been proposed before.",
author = "Chen, {Shung Chih} and Jer-Min Jou",
year = "1997",
month = "12",
day = "1",
doi = "10.1109/43.594835",
language = "English",
volume = "16",
pages = "299--308",
journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",
issn = "0278-0070",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "3",

}

TY - JOUR

T1 - Diagnostic fault simulation for synchronous sequential circuits

AU - Chen, Shung Chih

AU - Jou, Jer-Min

PY - 1997/12/1

Y1 - 1997/12/1

N2 - In this paper, a time and memory-efficient diagnostic fault simulator for sequential circuits is first presented. A distributed diagnostic fault simulator is then presented based on the sequential algorithm to improve the speed of the diagnostic process. In the sequential diagnostic fault simulator, the number of fault-pair output response comparisons has been minimized by using an indistinguishability fault list that stores the faults that are indistinguishable from each fault. Due to the symmetrical relationship of the fault-pair distinguishability, fault list sizes are reduced. Therefore, the different diagnostic measures of a given test set can be generated very quickly using a small amount of memory. To further speed up the process of finding the indistinguishable fault list for each fault, a distributed approach is proposed and developed. The major idea for this approach is that each processor constructs the indistinguishable fault lists for a certain percentage of faults only. Experimental results show that the sequential diagnostic fault simulator runs faster and uses less memory than a previously developed one and that the distributed algorithm even achieves superlinear speedup for a very large sequential benchmark circuit, s35932. To the authors' knowledge, no distributed diagnostic fault simulation system for sequential circuits has been proposed before.

AB - In this paper, a time and memory-efficient diagnostic fault simulator for sequential circuits is first presented. A distributed diagnostic fault simulator is then presented based on the sequential algorithm to improve the speed of the diagnostic process. In the sequential diagnostic fault simulator, the number of fault-pair output response comparisons has been minimized by using an indistinguishability fault list that stores the faults that are indistinguishable from each fault. Due to the symmetrical relationship of the fault-pair distinguishability, fault list sizes are reduced. Therefore, the different diagnostic measures of a given test set can be generated very quickly using a small amount of memory. To further speed up the process of finding the indistinguishable fault list for each fault, a distributed approach is proposed and developed. The major idea for this approach is that each processor constructs the indistinguishable fault lists for a certain percentage of faults only. Experimental results show that the sequential diagnostic fault simulator runs faster and uses less memory than a previously developed one and that the distributed algorithm even achieves superlinear speedup for a very large sequential benchmark circuit, s35932. To the authors' knowledge, no distributed diagnostic fault simulation system for sequential circuits has been proposed before.

UR - http://www.scopus.com/inward/record.url?scp=0031095828&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0031095828&partnerID=8YFLogxK

U2 - 10.1109/43.594835

DO - 10.1109/43.594835

M3 - Article

AN - SCOPUS:0031095828

VL - 16

SP - 299

EP - 308

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

SN - 0278-0070

IS - 3

ER -