Digital offset trimming techniques for CMOS MEMS accelerometers

Po Chang Wu, Bin Da Liu, Sheng Hsiang Tseng, Hann Huei Tsai, Ying Zong Juang

研究成果: Article同行評審

20 引文 斯高帕斯(Scopus)

摘要

This paper presents a digital trimming technique for canceling the output offsets caused by sensor mismatches in an accelerometer design. The offset cancellation techniques provide fine trimming steps with higher chip area efficiency compared with that of conventional capacitor array compensation approaches. The accelerometer, fabricated in a 0.18-μm complementary metal-oxide-semiconductor micro-electro-mechanical-system process, containing the micro-mechanical structure and readout circuits, occupies only a 0.64 × 0.9 mm2 area. The chip draws 0.4 mA from a 1.8-V supply. The measured sensitivity is 195 mV/g and the nonlinearity is 0.78% within the ± 12 g sensing range. The output noise floor is 150 μ/√Hz, corresponding to a 1-g 100-Hz sinusoidal acceleration. The output offset voltage can be trimmed from several tens to several hundreds of millivolts down to several millivolts.

原文English
文章編號6617702
頁(從 - 到)570-577
頁數8
期刊IEEE Sensors Journal
14
發行號2
DOIs
出版狀態Published - 2014 二月

All Science Journal Classification (ASJC) codes

  • 儀器
  • 電氣與電子工程

指紋

深入研究「Digital offset trimming techniques for CMOS MEMS accelerometers」主題。共同形成了獨特的指紋。

引用此