Double-gate CMOS evaluation for 45nm technology node

Meng-Hsueh Chiang, Judy X. An, Zoran Krivokapic, Bin Yu

研究成果: Conference contribution

摘要

Performance of Double-Gate (DG) CMOS is evaluated via device and SPICE circuit simulation using a physical compact model and a look-up table (LUT) model approach. In this work, LUT models are generated for the first time for DG MOSFETs at ITRS 45nm technology node. A physical compact model is further used for device scaling and sensitivity study. It is essential to project what benefits DG device can offer, and, on the other hand, to assess the pragmatic design issue in circuit implementation when parasitic has to be included. We facilitate SPICE simulation to address the DG device performance advantages over conventional single-gate (SG) device at ITRS 45nm technology node. We also discuss whether and how much the DG benefits will be undermined by parasitic.

原文English
主出版物標題2003 Nanotechnology Conference and Trade Show - Nanotech 2003
編輯M. Laudon, B. Romanowicz
頁面326-329
頁數4
2
出版狀態Published - 2003
事件2003 Nanotechnology Conference and Trade Show - Nanotech 2003 - San Francisco, CA, United States
持續時間: 2003 二月 232003 二月 27

Other

Other2003 Nanotechnology Conference and Trade Show - Nanotech 2003
國家/地區United States
城市San Francisco, CA
期間03-02-2303-02-27

All Science Journal Classification (ASJC) codes

  • 工程 (全部)

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