Double-Gate MOSFETs with aymmetric drain underlap: A device-circuit co-design and optimization perspective for SRAM

Ashish Goel, Sumeet Gupta, Aditya Bansal, Meng-Hsueh Chiang, Kaushik Roy

研究成果: Conference contribution

9 引文 斯高帕斯(Scopus)

摘要

Over the past few decades, CMOS technology has mainly been driven by transistor scaling. However, the scaling benefits of conventional bulk MOSFETs come at the cost of increased short channel effects, degrading their performance as a switch. In order to counter such effects, device structures with enhanced gate control of the channel have been proposed [1]. A double-gate (DG) MOSFET is one such structure which has shown tremendous promise. Due to reduced junction capacitance in DG-MOSFETs, drain capacitance is mainly dominated by the overlap capacitance, which may be reduced by introducing an underlap between source/drain and channel. However, underlap on the source side leads to significant degradation in ON-current as well as increased effect of process variations on the threshold voltage. Hence, in this paper, we explore the design and optimization of DG-MOSFETs with underlap only on the drain side.

原文English
主出版物標題67th Device Research Conference, DRC 2009
頁面57-58
頁數2
DOIs
出版狀態Published - 2009 12月 11
事件67th Device Research Conference, DRC 2009 - University Park, PA, United States
持續時間: 2009 6月 222009 6月 24

出版系列

名字Device Research Conference - Conference Digest, DRC
ISSN(列印)1548-3770

Other

Other67th Device Research Conference, DRC 2009
國家/地區United States
城市University Park, PA
期間09-06-2209-06-24

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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